TWEPP-17 - (other twepp conferences)
11 - 14 September 2017
Santa Cruz, California
published March 20, 2018
Santa Cruz, California
published March 20, 2018
The workshop will cover all aspects of electronics for particle physics experiments, and accelerator instrumentation of general interest to users.
LHC experiments (and their operational experience) will remain a focus of the meeting but a strong emphasis on R&D for future experimentation will be maintained, such as SLHC, CLIC, ILC, neutrino facilities as well as other particle and astroparticle physics experiments.
The purpose of the workshop is :
- To present results and original concepts for electronic research and development relevant to experiments as well as accelerator and beam instrumentation at future facilitiest
- To review the status of electronics for the LHC experiments
- To identify and encourage common efforts for the development of electronics
- To promote information exchange and collaboration in the relevant engineering and physics communities.
Editorial Board
- Jean-Pierre Cachemiche
IN2P3 - Jorgen Christiansen
European Organization for Nuclear Research (CERN), Geneva, Switzerland - Władysław Dąbrowski
- Salvatore Danzeca
CERN - Christophe De La Taille
CENBG - P. Farthouat
European Laboratory for Particle Physics (CERN), Geneva - Marcus French
RAL - Alex Grillo
UCSC - Ping Gui
Souther Methodist University - Ferdinand Hahn
CERN - Geoff Hall
Imperial College London - Greg Iles
Imperial College - Alexander Kluge
European Organization for Nuclear Research (CERN) - Hansen Magnus
CERN - Alessandro Marchioro
CERN - Angelo Rivetti
Istituto Nazionale di Fisica Nucleare (INFN) - Sezione di Torino - Wesley Smith
University of Wisconsin-Madison (US) - S. Veneziano
Università di Roma I 'La Sapienza',Dipartimento di Fisica, Roma and I.N.F.N. Roma - Julie Whitmore
FNAL - Ken Wyllie
CERN
| ASIC |
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CBC3: a CMS microstrip readout ASIC with logic for track-trigger modules at HL-LHC
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A 2.56 GHz Radiation Hard Phase Locked Loop ASIC for High Speed Serial Communication Links
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Characterization of a 9-Decade Femtoampere ASIC Front-End for Radiation Monitoring
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An 8-Channel ASD in 130 nm CMOS for ATLAS Muon Drift Tube Readout at the HL-LHC
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Development of a Large Pixel Chip Demonstrator in RD53 for ATLAS and CMS Upgrades
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“ALTIROC0, a 20 pico-second time resolution ASIC for the ATLAS High Granularity Timing Detector (HGTD)”
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A 2 Gsps Waveform Digitizer ASIC in CMOS 180 nm Technology
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Characterization Measurement Results of MuTRiG - A Silicon Photomultiplier Readout ASIC with High Timing Precision and High Event Rate Capability
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ALICE SAMPA-ASIC Second-Prototype Qualification Studies for LHC Run 3 and Beyond
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Characterization of SLVS Driver and Receiver in a 65 nm CMOS Technology for High Energy Physics Applications
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MATISSE: a Low Power Front-End Electronics for MAPS Characterization
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A Digital Processing Unit of a Highly Integrated Receiver Chip for PMTs in JUNO
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Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors
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CAcT$\mu$S: High-Voltage CMOS Monolithic Active Pixel Sensor for Tracking and Time Tagging of Charged Particles
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Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC
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ASICs and Readout System for a multi Mpixel single photon UV imaging detector capable of space applications
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Prototype Chip for a Control System in a Serial Powered Pixel Detector at the ATLAS Phase II Upgrade
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Laboratory and Beam Test Results of TOFFEE ASIC and Ultra Fast Silicon Detectors
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Design and characterization of the monolithic matrices of the H35DEMO chip
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KLauS4: A Multi-Channel SiPM Charge Readout ASIC in 0.18µm UMC CMOS Technology
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Short-Strip ASIC (SSA): A 65nm Silicon-Strip Readout ASIC for the Pixel-Strip (PS) Module of the CMS Outer Tracker Detector Upgrade at HL-LHC
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Design and simulation of a 65 nm Macro-Pixel Readout ASIC (MPA) for the Pixel-Strip (PS) Module of the CMS Outer Tracker Detector at the HL-LHC
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Development of a Front-End ASIC for 1D Detectors with 12 MHz Frame-Rate
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Performance of CATIA ASIC, the APD readout chip foreseen for CMS Barrel ECAL electronics upgrade at HL-LHC
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Developments of Two High-speed Dual-channel VCSEL Driver ASICs
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LAPA, a 5 Gb/s modular pseudo-LVDS driver in 180 nm CMOS with capacitively coupled pre-emphasis
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A Monolithic HV/HR-MAPS Detector with a Small Pixel Size of 50 µm x 50 µm for the ATLAS Inner Tracker Upgrade
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A Low-Noise CMOS Pixel Direct Charge Sensor Topmetal-IIa for Low Background and Low Rate- Density Experiments
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A high-Precision Timing ASIC for TOF-PET Applications
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Design and Characterization of the Readout ASIC for the BESIII CGEM Detector
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Development of Depleted Monolithic Pixel Sensors in 150 nm CMOS technology for the ATLAS Inner Tracker Upgrade
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Monolithic Pixel Development in 180 nm CMOS for the Outer Pixel Layers in the ATLAS Experiment
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| Optoelectronics and Links |
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The VTRx+, an Optical Link Module for Data Transmission at HL-LHC
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| Other |
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DQM4HEP - A Generic Online Monitor for Particle Physics Experiments
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Adaption of an FPGA-based Sampling-ADC for the Crystal Barrel Calorimeter
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CERN-IPMC Solution for AdvancedTCA Blades
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| Packaging and Interconnects |
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Manufacturing experience and test results of the PS prototype flexible hybrid circuit of the CMS Tracker Upgrade
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| Power Grounding and Shielding |
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Serial Powering Optimization for CMS and ATLAS Pixel Detectors within RD53 Collaboration for HL-LHC: System Level Simulations and Testing
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ATLAS ITk Short-Strip Stave Prototype Module with Integrated DCDC Powering and Control
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Low Voltage Powering of On-Detector Electronics for HL-LHC Experiments Upgrades
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A 2.5V Step-Down DC-DC Converter for Two-Stages Power Distribution Systems
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| Production Testing and Reliability |
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The Development of Front-End Readout Electronics for ProtoDUNE-SP LAr TPC
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Quality Control Considerations for the Development of the Front End Hybrid Circuits for the CMS Outer Tracker Upgrade
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Electrical and Functional Characterisation with Single Chips and Module Prototypes of the 1.2 Gb/s Serial Data Link of the Monolithic Active Pixel Sensor for the Upgrade of the ALICE Inner Tracking System.
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Quad Module Hybrid Development for the ATLAS Pixel Layer Upgrade
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Electromigration driven failures on miniature silver fuses at the Large Hadron Collider
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A Multi-Channel PCI Express Readout Board Proposal for the Pixel Upgrade at LHC
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Functional Tests of 2S Modules for the CMS Phase-2 Tracker Upgrade with a MicroTCA-Based Readout System
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ATLAS ITk Short-Strip Stave Prototypes with 130 nm Chipset
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| Programmable Logic Design Tools and Methods |
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FED Firmware Interface Testing with Pixel Phase 1 Emulator
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The FEROL40, a microTCA card interfacing custom point-to-point links and standard TCP/IP
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Upgrade of the YARR DAQ System for the ATLAS Phase-II Pixel Detector Readout Chip
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Studies on the Readout of the ATLAS Inner Tracker 2 Using Commercial Networking HardwareStudies on the Readout of the ATLAS Inner Tracker Using Commercial Networking Hardware
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The New Version of the LHCb SOL40-SCA Core to Drive Front-End GBT-SCAs for the LHCb Upgrade
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Clock and Trigger Distribution for ALICE Using the CRU FPGA Card
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DRM2: the Readout Board for the ALICE TOF Upgrade
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New slow-control FPGA IP for GBT based system and status update of the GBT-FPGA project
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Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS
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| Radiation Tolerant Components and Systems |
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Radiation Hardness Studies and Evaluation of SRAM-Based FPGAs for High Energy Physics Experiments
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Fibre Optics Cabling Design for LHC Detectors Upgrade Using Variable Radiation Induced Attenuation Model
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Design and radiation tests on a LED based emergency evacuation directional lighting
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First irradiation test results of the ALICE SAMPA ASIC
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Effect of Gamma Irradiation on Leakage Current in CMOS Read-out Chips for the ATLAS Upgrade Silicon Strip Tracker at the HL-LHC
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A study of SEU-tolerant latches for the RD53A chip
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Measurements and Simulations of Single-Event Upsets in a 28-nm FPGA
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| Systems Planning Installation Commissioning and Running Experience |
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Readout Electronics for the First Large HV-MAPS Chip for Mu3e
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Next Generation ATCA Control Infrastructure for the CMS Phase-2 Upgrades
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ATLAS Phase-II Upgrade Pixel Data Transmission Development
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Readout Electronics System of the CASCA Front-End Chip for the TPC Based X-Ray Polarimeter
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Design of the New Front-End Electronics for the Readout of the Upgraded CMS Electromagnetic Calorimeter for the HL-LHC
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Design studies for the off-detector electronics of the upgraded CMS Barrel calorimeter for the HL-LHC
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Electronics and Firmware of the Belle II Silicon Vertex Detector Readout System
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The TrainBuilder Data Acquisition System for the European-XFEL
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ATCA - thermal management study for the ATLAS phase II upgrades
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Development of Telescope Readout System Based on FELIX for Testbeam Experiments
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Simulation of the ATLAS New Small Wheel Trigger System
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Commissioning and First Running Experiences with the TOP Barrel PID Detector in the Belle II Experiment
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Validation of the Front-End Electronics and Firmware for LHCb Vertex Locator.
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CMS DAQ Current and Future Hardware Upgrades up to Post Long Shutdown 3 (LS3) Times
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Demonstrating TTC-PON Robustness and Flexibility
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Integration of the CMS Phase 1 Pixel Detector
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Intelligence Elements and Performance of the FPGA-based DAQ of the COMPASS Experiment
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Software Defined Radio Based Readout of Microwave SQUID Multiplexed Metallic Magnetic Calorimeter Arrays
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| Trigger |
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An FPGA-based Track Finder for the L1 Trigger of the CMS Experiment at the HL-LHC
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Development of the jet Feature EXtractor (jFEX) for the ATLAS Level 1 Calorimeter Trigger upgrade at the LHC
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Development of a High-Throughput Tracking Processor on FPGA Boards
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A Real-Time Demonstrator for Track Reconstruction in the CMS L1 Track-Trigger System Based on Custom Associative Memories and High-Performance FPGAs
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The ATLAS Fast Tracker System
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A Multi-Level Triggering System for the Mini-EUSO UV Telescope
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Functionality and Performance of the ALFA_CTPIN Module
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Boosted Decision Trees in the CMS Level-1 Endcap Muon Trigger
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Data Analysis at Level-1 Trigger Level
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Development of the New Trigger Processor Board for the ATLAS Level-1 Endcap Muon Trigger for Run-3
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The Development of Global Feature eXtractor (gFEX) – the ATLAS Calorimeter Level 1 Trigger for ATLAS at High Luminosity LHC
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Simulations of Busy Probabilities in the ALPIDE Chip and the Upgraded ALICE ITS Detector
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Hardware Trigger Processor for the MDT System
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The ALICE Trigger System for LHC Run 3
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