Porting Lattice QCD benchmark to upcoming STX stencil/tensor accelerator
S. Schlepphorst* and S. Krieg
*: corresponding author
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Pre-published on: February 10, 2025
Published on:
Abstract
Developed under the European Processor Initiative (EPI), the STX stencil/tensor accelerator aims to
achieve a 5-10x higher energy efficiency over general purpose compute units.
The architecture consists of specialized MIMD compute units which are supported and controlled by
RISC-V cores.
We describe a co-design effort between hardware, software, and application development focused
around porting a LQCD benchmark to this new architecture.
DOI: https://doi.org/10.22323/1.466.0451
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