Single Event Effects introduce soft errors in ASICs. Design methodologies like Triple Modular
Redundancy (TMR) with clock skew insertion, a system level redundancy technique is a common
practice by designers to mitigate soft errors. However, the optimal spacing between memory
elements in a TMR in 65nm process hasn't been addressed so far. RD53SEU is a mini ASIC
development under the framework of the CERN RD53 collaboration to characterize the soft error
rates against the separation spacing and clock skew between memory elements in a TMR. This
article describes the architecture and design aspects of the various test structures on the RD53SEU
test chip.
Characterization of Soft Error Rate Against Memory Elements Spacing and Clock Skew in a Logic with Triple Modular Redundancy in a 65nm Process
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Pre-published on:
May 20, 2019
Published on:
July 25, 2019
Abstract
DOI: https://doi.org/10.22323/1.343.0029
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Copyright owned by the author(s) under the term of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
Copyright owned by the author(s) under the term of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.