The RD53 collaboration was established to develop the next generation of pixel readout chips needed by
ATLAS and CMS at the HL-LHC and requiring extreme rate and radiation tolerance. The 65 nm CMOS
process has been adopted in order to satisfy the high level of integration requirement. However, the SEU
immunity should be carefully considered for a deep submicron process like the 65 nm. Indeed, the device
dimensions are small and the capacitance of the storage nodes becomes very low. A chip prototype
including different SEU tolerant structures was designed in a 65 nm technology. Several proton
irradiation tests were carried out in order to estimate the SEU tolerance of the proposed structures and the
level of improvement comparing with a standard architecture.