PoS - Proceedings of Science
Volume 313 - Topical Workshop on Electronics for Particle Physics (TWEPP-17) - ASIC
Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors
L. Gaioni, D. Braga*, D.C. Christian, G. Deptuch, F. Fahim, B. Nodari, L. Ratti, V. Re and T.N. Zimmerman
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Pre-published on: March 05, 2018
Published on: March 20, 2018
Abstract
This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided.
DOI: https://doi.org/10.22323/1.313.0021
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