For the High-Luminosity LHC, planned to start in 2027, the ATLAS experiment will be equipped with the Hardware Tracking for the Trigger (HTT) system, a dedicated hardware system able to reconstruct tracks in the silicon detectors with low latency. The HTT will be composed of about 700 ATCA boards, based on new technologies available on the market, like high speed links and powerful FPGAs, as well as custom-designed Associative Memory ASICs, which are an evolution of those developed for the ATLAS Fast Tracker. The HTT is designed to cope with the expected extreme high luminosity in the so-called L0-only scenario, where the HTT will operate at the L0 rate (1 MHz). It will provide good quality tracks to the software High- Level-Trigger (HLT), operating as coprocessor to lighten the load of the software tracking. The implementation of the HTT allows the HLT farm size to be reduced by a factor of 10. All ATLAS sub-detector systems are designed also for an evolved, so-called "L0/L1", architecture, where part of the HTT is used in a low-latency mode (L1Track), providing tracks in regions of ATLAS at a rate of up to 4 MHz, with a latency of a few micro-seconds. This evolved architecture poses very stringent requirements on the latency budget and to the dataflow rates. All the requirements and the specifications of this system have been assessed. The design of all the components has been reviewed and validated with preliminary simulation studies. Soon, the development of the first prototypes will start. In this paper we describe the status of the HTT design, discuss the challenges and assessed specifications, towards the preparation of the first slice tests with real prototypes.