To cope with increased radiation levels expected at the HL-LHC new approaches are being investigated using monolithic CMOS pixel detectors where readout electronics and depleted charge collection layer are combined. Those devices rely on radiation hard process technology, multiple nested wells, high resistivity substrates and ability to apply high voltage bias to achieve significant depletion depths. They can be thinned and backside processed for biasing. Since 2014, members of more than 20 groups in ATLAS are collaborating in CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterization with the goal to demonstrate that depleted CMOS pixels are suited for high rate, fast timing and high radiation operation at LHC. Many CMOS technology vendors have been approached in this effort. This presentation introduces challenges for the usage of CMOS pixel detectors at HL-LHC and gives a summary of different concepts and the current state of designs of depleted CMOS prototypes.